The present invention relates to information handling systems, and more particularly to error detection and recovery during direct memory access of memory in personal computer systems.
Generally in computer systems and especially in personal computer systems, data are transferred between various elements such as a central processing unit (CPU), memory devices and direct memory access (DMA) control circuitry as well as expansion devices such as input/output (I/O) adapters, bus controllers (i.e., elements which can control the computer system), bus slaves (i.e., elements which are controlled by bus controllers). The expansion devices are often interconnected via a system I/O bus. The DMA control circuitry is used to transfer information to and from memory devices without using the CPU; generally, once the CPU has provided the DMA control circuitry with control information such as the base location from where information is to be moved, the address of where the data information should go, and the size of the data information to be moved, the DMA control circuitry controls the transfer of the data information.
Often in computer systems it is necessary for expansion devices to arbitrate for ownership of the I/O bus of the computer system; i.e., to decide which expansion device may transfer information via the I/O bus. For the purposes of arbitration the DMA controller is treated as if it is an expansion device such that the DMA controller must arbitrate with other expansion devices in order to win permission to transfer information via the I/O bus. It is known to provide an arbiter which determines which expansion device may transfer information via the I/O bus. Such an arbiter serves as a central arbitration control point via which all arbitration for the I/O bus occurs.
The I/O bus operates in time divided units which are called bus cycles. Bus cycles of the I/O bus are divided into arbitration cycles and grant cycles. During arbitration cycles, expansion devices compete for ownership of the I/O bus. During grant cycles, a device which has won ownership of the bus, transfers information. Normally, during arbitration cycles, information is not transferred via the bus. However, it is known to perform refresh operations, in which the memory of the system is refreshed, during arbitration cycles.
One way of initiating an arbitration cycle is by an expansion device which desires to transfer information via the bus generating a preempt signal. When the preempt signal is received by the expansion device which currently owns the bus it causes the device to relinquish its control so that another arbitration cycle may occur.
It is known to provide a computer system with the ability to determine whether an error condition has occurred during operation. Generally, when an error condition occurs, the computer system will cease operation (i.e., crash) because the error condition causes uncertainty in the information which the computer system is processing. An example of an error condition is a bus timeout where a device which owns the bus will not relinquish control of the bus causing the computer system to force the device to relinquish control of the bus.